Flexible SoC Verification Enviroment
Our experience in the functional verification of FPGA designs for complex systems, allowed us to develop a simulation framework for a quickly construction of a complete testbench, facilitates communication with standard interfaces and automates the execution of test cases and result analyzing. The architecture of the framework allows adding signal generators and recorders outputs a simple and scalable manner .
This framework allows us to ensure that the FPGA implementation of our clients corresponds to the specification of the system design to shortly verify.
In our proyects, we lead the overall verification process, from test plan definition, to testbench implementation, DUV simulation and bug tracking. The verification environment is develop in System Verilog as a new instance of our continuously improved framework. The UVM base library is employed for the testbench architecture and in-house developed verification IPs (Agents) where integrated and reused. SV classes are extensively used to manage a complex Loosely Timed reference model that involves an instruction level simulator for the CPU and allows emulating all the high level transactions derived from ambitious functional coverage requirements.