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Advanced Verification Enviroment Development for SoC

This project consisted in the Verification of the System On Chip (SoC) designed to be the main controller of a Critical System and implemented into a multimillion gate FPGA. The SoC incorporates a general purpose processor, several application specific cores and controllers; all connected with a multi-master AXI bus and fault detection & recovery resources. It also handles several dedicated interfaces with stringent timing constraints, as well as standard IO for DRAM, SRAM, Ethernet, USB and I2C interfaces.

Emtech lead the overall verification process, from test plan definition, to testbench implementation, DUV simulation and bug tracking. The verification environment was developed in System Verilog as a new instance of our continuously improved framework. The UVM base library was employed for the testbench architecture and in-house developed verification IPs (Agents) where integrated and reused. SV classes were extensively used to manage a complex Loosely Timed reference model that involves an instruction level simulator for the CPU and allows emulating all the high level transactions derived from ambitious functional coverage requirements.

• Object Oriented Programming based Testbench.

• Scalable 

• Maintainable

• Reusable.

• Advanced Test Design & Coverage Analysis.

Upper view
Lower view
Dimensions

ID Date Type Name Descripcion
Brochure Ver 2015 documentation Brochure Emtech Core Verification Brochure Emtech Core Verification