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Defense

Emtech has wide experience in the development of processing modules for radar systems, both primary and secondary, we have participated in projects from the design, implementation of radar systems.

Among the main tasks we have done include:

  • Design of FPGA core for pre - processing of radar signals .
  • Block signal generator for radar control and sync .
  • Simulators for secondary radar transponder .
  • Implementation on FPGA filter banks .
  • FPGA Cores for capturing, processing , packaging, and data generation.
  • Integrating block power estimate calculation during monitoring periods and JATS whose results produce special packages besides the normal data .
  • Sending packets of data to a PC via DMA through the PCIe interface to test a synthesizing radar operation , especially the acquiring and processing SW .
  • Using PCIe interface to send a plate of Innovative X5 -TX data baseband signals .
  • Implementing a core that performs the interpolation and frequency shift data and sends them to the DACs to generate the analog signals with the chain digitization and processing of TPS tested.
  • Digital processing for radar antenna emulation

Aircraft Radar Simulator

We developed a signal and target generator for primary and secondary radar transponder, which allows radar calibration and configuration. All the processing and data storage was carried out with an FPGA and adquisition radar board.

 

Hardware Design for Radar

  • Experience in the design of backplane
  • Adaptor levels
  • Boards with FPGA for processing
  • Communications (RS -485 , MIL- 1553 , RS -232 , etc.) .
  • Management controlled impedance lines
  • Digital data buses .

Designs for Radar Cores

  • Design of FPGA CORES for capturing, processing , packaging, and data generating radar signals.
  • Generator block control signals and sync .
  • Simulator target responses for secondary radar.
  • Implementation on FPGA filter banks for detection of primary radar interference .
  • CORE Development of synthesizing plate responses to primary radar pulses to test the performance of chains acquisition and processing SW .
  • Processing digital emulation antenna synthetic aperture radar (SAR ) .
  • Integration calculation block power estimation during periods of monitoring and JATS .
  • Using CORES PCIe interface for transmitting high-speed data between the PC and the boards acquisition or synthesis of radar signals.

 

Operation Interface

  • Programming a remote operator interface to a microcontroller radar system that allows the activation and deactivation of RF and IFF by several operators .
  • Programming microcontrollers boards connected via Ethernet modules

ID Date Type Name Descripcion
Brochure D&A 2013 documentation Brochure Defensa y Aeroespacial